/*******************************************************************
* Copyright (C) 2022 Xilinx, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xzdma.h"

/*
* The configuration table for devices
*/

XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] =
{
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_0_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_0_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_0_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_0_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_1_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_1_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_1_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_1_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_2_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_2_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_2_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_2_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_3_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_3_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_3_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_3_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_4_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_4_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_4_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_4_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_5_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_5_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_5_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_5_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_6_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_6_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_6_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_6_IS_CACHE_COHERENT
	},
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_7_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_7_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_7_DMA_MODE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_ADMA_7_IS_CACHE_COHERENT
	}
};
